1. Field of the Invention
The invention relates to a pixel structure, an active device array substrate having the pixel structure, and a flat display panel.
2. Description of Related Art
With increasing progress towards display technologies, displays facilitate our daily lives, and the requirements for light and compact displays contribute to development of flat panel displays (FPDs) as the mainstream displays at this current stage. In general, each pixel structure in an FPD includes an active device and a pixel electrode, and the active device serves as a switch element of a display unit. To control each individual pixel structure, a certain pixel is usually selected by a corresponding scan line and a corresponding data line, and display data corresponding to the certain pixel are displayed through providing an appropriate operating voltage. The pixel structure further includes a storage capacitor that stores the afore-mentioned operating voltage, such that the pixel structure can retain the voltage in order to stabilize the display images.
Devices in the FPD operated under a high voltage may have increasing current leakage, and therefore two thin film transistors (TFTs) are often connected in series, so as to reduce the current leakage.
FIG. 1 is a schematic view illustrating circuits of two serially-connected TFTs in a conventional pixel structure. The conventional pixel structure P includes a first thin film transistor TFT1, a second thin film transistor TFT2, a storage capacitor Cst, and a display capacitor (e.g., an electro-phoretic capacitor or a liquid crystal capacitor CLC). Here, the first thin film transistor TFT1 and the second thin film transistor TFT2 are serially connected to each other. The gate electrode of the first thin film transistor TFT1 and the gate electrode of the second thin film transistor TFT2 are electrically connected to the same scan line SL, and the first thin film transistor TFT1 is electrically connected to the data line DL. The second thin film transistor TFT2 is electrically connected to the storage capacitor Cst and the liquid crystal capacitor CLC.
As mentioned above, the devices in the FPD operated under a high voltage may have increasing current leakage. In order to reduce the current leakage, the layout area of the common electrode in the pixel structure is often expanded to increase the storage capacitance of the storage capacitor Cst. However, to ensure satisfactory electrical performance of the pixel structure P (e.g., to reduce the current leakage and increase the conductive current), the layout design of two serially-connected TFTs needs to be applied in the pixel structure P. The increasing number of TFTs leads to reduction of the usable area of the storage capacitor Cst, and thus the storage capacitance of the storage capacitor Cst cannot be increased. On the other hand, if the layout area of the first thin film transistor TFT1 and the second thin film transistor TFT2 are reduced and the layout area of the common electrode is expanded for increasing the storage capacitance of the storage capacitor Cst, the electrical performance of the devices may be deteriorated. For instance, the process shift between the gate electrode and the source electrode and drain electrode results in the change of parasitic capacitance, and thus the display images may flicker. Accordingly, how to expand the layout area of the storage capacitor Cst and maintain satisfactory performance of devices is one of the issues to be resolved immediately.